Eridan is a rapidly-growing startup located in California and Zagreb, building 5G radios to enable abundant wireless connectivity everywhere in the world. Our MIRACLE™ transceiver uses a polar modulator at its output, features a decade of software-controlled tunability with high wall-plug efficiency independent of output power, and unprecedented linearity; there is nothing like it in the entire world. We aspire to put an Eridan transceiver in every wireless device in the world. The address of the office is Eridan Communications d.o.o., Ulica Labvoslava Ružičke 32, HR-10000 Zagreb, Croatia.
Eridan is currently building out our digital design team. As an FPGA/ASIC Design Engineer (DSP), You will focus on digital signal processing (DSP) and digital communication system blocks as part of complex FPGA SoC products and will participate in numerous exciting and challenging activities in a fast-moving design environment.
In this role, you will,
- Design, implement and integrate 5G Protocol Stack layers from source models, along with block-level micro-architecture design, RTL coding, simulation, and documentation.
- Learn how to migrate from RTL to ASIC.
- Take responsibility for area/power optimization and design trade-off analysis, as well as block and chip-level synthesis and timing closure.
- Provide chip bring-up and silicon validation support.
- Script and automate workflows in Python, Tcl, and GNU Make.
- Learn about and get experience in state-of-the-art communications technology, hardware, and test equipment.
Qualities of a successful candidate:
- Master’s degree in electrical engineering, computer engineering, or another engineering discipline.
- Has strong technical and analytical skills and be comfortable working and solving problems independently as well as collaboratively within a team. We look for engineers with initiative, persistence, curiosity, and good communication skills.
- 2+ years of experience working with one of the following: (i) computer and embedded system architectures, (ii) Vivado for FPGA development, (iii) SystemVerilog, Verilog, or VHDL RTL design for synthesis and verification
- Experience in scripting and programming languages in two or more of the following: MATLAB, Python, C/C++, Perl, Tcl, Make, Bash
Extra points if you have experience with one or more of the following:
- design verification (DV)
- Designing DSP or digital communication system data path blocks (e.g. filters, transforms, PHY blocks, loops, FEC)
- Familiarity with a Continuous Integration Tool
- ASIC synthesis
What’s cool about working at Eridan:
- Flexible hybrid remote work policy.
- Opportunity to work with an international team of engineers and computer scientists on a technologically challenging and unique communications system.
- Be directly involved in converting an idea into a qualified product.
Eridan is an equal opportunity employer. We value and celebrate diversity and are committed to creating an inclusive environment for all employees. Qualified applicants will be considered for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability, or protected veteran status. To be employed, the candidate must be a citizen of the European Union or the United States of America.